Method of transferring information

ABSTRACT

A method of transferring information via a time-switched connection which extends via at least one first time channel with which a channel interval of a first cycle is associated, a synchronizer, a data register and a second time channel with which a channel interval of a second cycle is associated. For the loss-free transfer of the information to an information receiver the data register is read out at least three times in a nondestructive manner in each second cycle, the original information being derived from the multiple information thus obtained by elimination of the excess of information.

United States Patent [191 [11] 3,824,349 Buchner July 16, 1974 F I3,676,599 7/1972 Heetman 1 79/15 BS INFORMATION [75] Inventor: RobertBertold Buchner, Hilversum, Primary Examiner-Ralph Blakeslee N h l dAttorney, Agent, or Firml rank R. Trifari; Simon L. [73] Assignee: U.S.Philips Corporation, New Cohen York, NY.

[22] Filed: July 23, 1973 [57] ABSTRACT PP 381,755 A method oftransferring information via a time- Related Us. Appncation Dataswitched connection which extends via at least one [63] C f S N 221 234J 27 1972 first time channel with which a channel interval of a 52 2 215 0 first cycle is associated, a synchronizer, a data register r and asecond time channel with which a'channel inter- [52] U S Cl 179/15 BS178/69 5 R 179/15 BY val of a second cycle is associated. For theloss-free [51] H04j 3/06 transfer of the information to an informationreceiver [58] Fieid BY the data register is read out at least threetimes in a 179/15 A 17/69 5 non-destructive manner, in each secondcycle,. the original information being derived from the multiple 56]References Cited information thus obtained by elimination of the excessof information. UNITED STATES PATENTS t- 3,632,883 1/1972 Aagaard 179/15AQ 2 Claims, 10 Drawing Figures 101-1 102-1 104 -1 [107 DATA STORESYNCHRONIZERS 03-1 108 a l 101-8 106 100-8 l/ MULTIPLEXER CYCL'CSIGNALLING STORE INFORMATION STORE Pmmmm 6 m4 DCBA SHEEI30F3 AAA DDD

2B'AA seas SCBB' vccs sccc

Fig.5

Fig.6

METHOD OF TRANSFERRING INFORMATION This is a continuation of applicationSer. No. 221,234, filed Jan. 27, 1972, now abandoned.

The invention relates to a method of transferring in formation via atime-switched connection. The connection extends via at least a firsttime channel with which a channel interval of a first cycle of channelintervals is associated. The information is also transferred through asynchronizer, a data register and a second time channel with which achannel interval of a second cycle of channel intervals is associated.The nominal duration of said second cycle is equal to the nominalduration of the first cycle. The synchronizer transfers the informationreceived via the first time channel to the data register in channelintervals of the second cycle. The position of the latter channelintervals in the second cycle is changed in accordance with the phasedifference between these channel intervals and the channel intervals ofthe first time channel.

This method is used in telecommunication exchanges in which connectionsare established between channels of pulse code modulation time-divisionmultiplex transmission systems. The data register which is permanentlyassociated with the first time channel determines the location in spaceof the first time channel. By reading out this register in the channelintervals of the second time channel a (time-switched) connection ismaintained between the first and the second time channel. In aconnection of this kind information may be lost if the data register iswritten in at a rate which is higher than the rate which it is read out.The rate in which writing in takes place is dependent upon the rate atwhich the information of the first time channel is received, while therate of readout is determined by the clock of the telecommunicationexchange. In a nominal sense these two rates are the same, but they mayacquire an unlimited phase difference in .nonsynchronizedtelecommunication systems, so that it may occur that from time to timeinformation is written in twice in succession without information beingread out in between. The information which is first written in is thenlost. I

The invention has for its object to prevent loss of information intime-switched connections of this kind. This is of special importance ifthe first time channel is a so-termed common signalling channel.

The method according to the invention is characterized in that for theloss-free transfer of the information to an information receiver, thedata register is read out at least three times in a non-destructivemanner in each second cycle, the original information being derived fromthe multiple information thus obtained by elimination of the excessinformation.

In order that the invention may be readily carried into effect, oneembodiment thereof will now be described in detail, by way of example,with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 shows a block diagram of a portion of a telecommunicationexchange using pulse code modulation and time-division multiplex,

FIGS. 2a-2c show some time diagrams for illustrating the operation ofthe portion of the telecommunication exchange shown in FIG. 1,

FIGS. 3a-3c show corresponding time diagrams for illustrating the methodaccording to the invention,

FIG. 4 shows an example of a logic diagram of a device for eliminatingthe excess of information, and

FIGS. 5 and 6 show tables for illustrating the operation of the deviceshown in FIG. 4.

The problem of the loss-free transfer of information via time-switchedconnections, using independent clocks in different parts of theconnections, will be described with reference to FIG. 1. This Figureshows a portion of a telecommunication exchange in which time-switchedconnections are established between receive channels and send channelsof PCM transmission systems with time-division multiplex. Each PCMsystem comprises a receive highway and a send highway, each of whichcomprises n one-way channels, each channel utilizing a different timeinterval (channel interval) of a cycle of time intervals. In the presentcase it will be assumed that n 32. In FIG. 1 the references 100-1 and100-8 denote the first and the eighth receive highway of a group ofeight PCM systems.

Information is transferred via a PCM highway in frames,each of which isdivided into 32 character locations, each character location beingdivided into, for example, 8 bit locations. Accordingly,'the time on aPCM highway is divided into time frames, each of which comprises 32channel intervals, each channel interval being divided into 8 bitintervals.

The telecommunication exchange under consideration has a cycle whichcomprises more time intervals than the cycle of a PCM highway. Thenumber of channels of an internal PCM highway of the telecommunicationexchange is accordingly larger. In particular, the telecommunicationexchange under consideration has a cycle of 16 X 32 512 time intervals,which means that the number of time intervals of a cycle is twice aslarge as the number of channels of a group of eight external PCMhighways. In the exchange the 8-bit characters are transferred inparallel form, utilizing seriesparallel converters at the receive sideand parallelseries converters at the send side of the exchange. Theconverters provide the adaptation between the transfer in series form onthe external PCM highways and the transfer in parallel form on theinternal PCM highways of the exchange. Each of the 512 time intervals ofa cycle of the telecommunication exchange determines a channel intervalon each of the internal PCM highways.

The telecommunication exchange also determines the channel intervals onthe send highways of the connected PCM transmission systems; for thispurpose the cycle of the exchange is divided into 32 main timeintervals, each of which comprises 16- of the previously mentioned 512time intervals, the latter being referred to hereinafter as sub-timeintervals. Consequently, each sub-time interval determines an (internal)channel of each internal PCM highway, and each main time intervaldetermines an (external) channel of each external send highway.

The receive highways -1 and 100-8 terminate in the synchronizers 101-1and 101-8, respectively, which convert the received informationcharacters to the time scale of the telecommunication exchange.Simultaneously with this conversion in time, the characters areconverted from the series to the parallel form for each character thechannel number is determined.

The synchronizers used are devices of known construction and'operation.Consequently, the operation of these devices will be described only inas far as it is of importance for understanding the present invention.

registers. The received characters are cyclically distributed over thecharacter registers by a first distributor under the control of areceive clock which supplies clock signals which are synchronized withthe bits, the

characters and the frames of the receive highway. The characters areread out of the receive buffer in main time intervals under the controlof the clock of the exchange. The character registers are read out by asecond distributor in a cyclical manner and in the same sequence asduring writing in. The bits of a character are read out simultaneouslyso that each character read out has the parallel form. The read-outcharacters are applied to an input highway of the telecommunicationexchange, the said input highway being denoted in FIG. 1 by thereferences 102-1 and 102-8, respectively.

The channel numbers are determined by counting the read-out charactersmodulo-32. The receive clock gives an indication as regards thebeginning of each receive cycle. The indication is stored in a flip-flopfrom which it is read out by the central clock with the same relativetime delay as is caused by the receive buffer in the transfer of thecharacters. The indication which is read out of the flipflop is usedfor-synchronizing a modulo-32 counter to the beginning of the cycle ofthe receive highway. Each time that a character is read out, the countercontents are increased by one so that for each read-out character theassociated channel number is generated. The channel numbers are appliedto a number highway which is denoted in FIG. 1 by the references103-1and 103-8, respectively.

In asynchronous telecommunication systems each exchange has a clockwhich is independent of the clocks of the other exchanges. As a result,no upper limit exists as regards the phase difference between theclocks. in the telecommunication exchange under consideration the phasedifference between the central clock and a receive clock may reach anyvalue. The receive buffer of the synchronizer can compensate for only alimited phase difference.

in the synchronizer the phase of the first distributor is compared withthe phase of the second distributor.

The first distributor has a cycle of four channel intervals of thereceive clock, while the second distributor has a cycle of four maintime intervals of the central clock. Due to differencesin the speed ofthe receive clock and of the central clock, differences will occurbetween the cyclic speeds of these distributors. By

measuring the phase difference between two distributors it is determinedwhether the phase difference is liable to decrease below a criticalvalue. This critical value is the value at which writing and reading aresimultaneousl y effected in one and the same channel register. Beforethe said critical value is reached, a correction signal is generated andthe phase of the second distributor is corrected. If, the firstdistributor gains on the second distributor, then after the correctionsignal the second distributor is advanced one additional step,corresponding to a decrease of the duration of one of the cycles thereofwith one main time interval. One character is then skipped duringreading. However, if the second distributor gains on the firstdistributor, the second distributor is held after the alarm .so that itperforms a ration of one of the cycles thereof with one main timeinterval. During the step in place the character of the characterregister indicated by the second distributor is read out once more.

The channel number counter is synchronized by making it perform anadditional step or a step in place, respectively, simultaneously withthe second distributor. The characters are then applied to the inputhighway and the number highway with the correct channel numbers at alltimes.

Hereinafter it will be assumed that the instants at which the phase ofthe second distributor is corrected are chosen to be such that onlycharacters of the synchronization channel, which may be the channelhaving the number 32, can be skipped. In this way no informationcharacters are lost.

The input highways 102-1 and 102-8 and the number highways 103-1 and103-8 terminate in a multiplexer 104 having a cycle of one main timeinterval. The output of multiplexer 104 is formed by an internal highway105 and an internal number highway 10.6 which terminate in a data store107. The multiplexer 104 connects the input highway 102-1 to theinternal highway 105 in the first sub-time interval of each main timeinterval, and simultaneously connects the number highway 103-1 to theinternal number highway 106. In the second sub-time interval of eachmain time interval the multiplexer establishes the correspondingconnections for the second receive highway of the group of eight, and soon in the third to the eighth sub-time interval inelusive of each maintime interval. In this way eight of the sixteen sub-time intervals ofeach main time interval are used for transferring the characters fromreceive highways -1 to 100-8 to the data store 107. The remaining eightsub-time intervals of each main time interval can be used forother'purposes or may be left unused.

The data store 107 comprises 256 data registers, i.e. one register foreach channel of a group of eight receive highways. Each of theseregisters is capable of storing one character and can be addressed by achannel number. The data store 107 stores each character which isreceived from the internal highway in the register which is addressed bythe channel number which is received from the internal number highway106. The output of the data store 107 is formed by the internal highway108.

a step in place," corresponding to an increase of the du- The data store107 is controlled by a cyclic store 109 having 512 store locations, i.e.one store location for each channel of the internal highway 108. Bystoring a channel number in a chosen location of store 109, the registerof the data store 107 corresponding to this channel number is read outonce every cycle, and the read-out character is applied to the internalhighway 108 in the sub-time interval (channel interval) corresponding tothe chosen store location. in this way a (time-switched) connection canbe maintained between each channel of the relevant group of eight re-The repetition period on the internal highway 108 of the charactersoriginating from one and the same receive channel is always equal to onecycle of the central clock. Due to the differences between therepetition periods on the internal highways 105 and 108, characters willoccasionally be skipped in the data store or will be read twice,respectively. In order to illustrate this aspect, a simplified systemwill be considered, comprising a group of 3 receive highways, each ofwhich comprises 4 channels and having a cycle of 24 sub-time intervals.

It is assumed that a character is written in the data store in the firsthalf of a sub-time interval, and is read out of the data store in thesecond half of a sub-time interval. Under consideration is a series ofcharacters A, B, C, D, originating from one and the same receivechannel. FIG. 2a illustrates the instants at which the characters arewritten in thedata store 107. The character A is written in in the firstsub-time interval of the first main time interval of the cycle of thecentral clock. This sub-time interval is denoted by 1.1 in the FIG. 2a.In general, the reference i. j. denotes the j" sub-time interval of thei' main time interval. It is assumed that the register of the data storecorresponding to the receive channel under consideration is read out inthe sub-time interval 1.5. Consequently the character A is read out inthe sub-time interval 1.5 following the sub-time interval 1.1 in whichthe character A is written in, as is illustrated in FIG. 2b. Thecharacter B will normally be written in in the sub-time interval 1.1 ofthe next cycle. However, it is assumed that the repetition period hasbeen prolonged by one main time interval, so that the character B iswritten in in the sub-time interval 2.1. In the preceding sub-timeinterval 1.5 the character A is read out again, assuming that thecharacters are read out from the data store in a non-destructive manner.In the sub-time interval 1.5 of the next cycle the character B is readout, in the sub-time interval 1.5 of the next cycle the character C isread out, and so on.

FIG. 3 illustrates the case where a character is skipped due to areduction of the repetition pe5iod. Again a series of characters A, B,C, D, originating from one and the same receive channel, is considered.FIG. 3a illustrates the instants at which the characters are written inthe data store. The character A is written in in the sub-time interval1.1. It is assumed that the register of the receive channel underconsideration is read out in sub-time interval 3.5. In the sub-timeinterval 3.5 which follows the sub-time interval 1.1 in which thecharacter A is written in, the character A is read out as is illustratedin FIG. 3b. The character B will normally be written in in the sub-timeinterval 1.1 of the.

next cycle. However, it is-assumed that the repetition period is reducedby one main time interval so that the character B is already written inthe sub-time interval 4.1 of the same cycle. The character B is read outin the sub-time interval 3.5 of the next cycle. The character C iswritten in in the sub-time interval 4.1 of this cycle. The character Dis normally written in in the sub-time interval 4.1 of the next cycle.However, it is assumed that the repetition period is again reduced byone main time interval, so that the character D is written in in thesub-time interval 3.1 of this cycle. The character D is and the channelsof the internal highway 108. Whether or not a connection is affected bya phase correction will depend on the relative positions of the sub-timeintervals in which writing in the reading out take place in the datastore for the connection. For example, FIG. 3 clearly shows that therelevant connection is not affected by the first phase correction whichresults in a shift of the sub-time interval for writin g in thecharacter B. The character is lost only after the second phasecorrection, which results in a shift'of the sub-time interval forwriting in the character D. In the simplified system comprising only 4channels per receive highway, a character is skipped or is transferredtwice, respectively, in each connection after 4 phase corrections in thesame direction. In the system used in practice each connection isaffected once after 32 phase corrections in the same direction,corresponding to a phase shift between the cycle of the receive highwayand the cycle of the central clock of 360 or one frame. If stable clocksare used in the exchanges, the frequency at which an error occurs errorto be understood to mean in this. case the loss of a character or theadditional occurrence of a character, respectively is very low. Duringthe transfer of speech signals these errors are hardly noticeable. Aproblem arises if data are transferred via a connection.

For transferring signalling information, modern telephone systems makeuse of a so-termed common signalling channel via which the signallinginformation is transferred in the form of coded messages. In PCM systemuse is made of a given time channel for this purpose. For thissignalling channel it is desirable that the information is transferredwithout loss. In FIG. 1 the reference 110 denotes a signallinginformation store which is connected to the internal highway 108 andwhich acts as the receiver and the buffer of the signalling informationwhich is supplied, by the signalling channels of the group of receivehighways -1, 100-8. The connections between the signalling channels onthe one side and the store on the other side extend via the data store107 in the same manner as the speech connections.

In order to preventsignalling characters from being lost due-to phasecorrections, the invention proposes that each register of the data store107 which corresponds to a signalling channel is read out in each cycleof the central clock three times with intervals of at least one maintime interval. Each read-out character is transferred to the store 110.Normally, each signalling character is then transferred'three times tothe store 110 and, due the phase corrections, this number isoccasionally increased or decreased by one, respectively, so that, forexample, a series of signalling characters R, S, T, U, originating froma signalling channel changes into the modified'series R, R, R, S, S, S,S, T, T, T, U, U, U, or into the series R, R, R, S, S, T, T, T, U, U, U,The latter series can be restored to the former series by a simple logicoperation.

The foregoing is illustrated in the FIGS. 20 and 30 for the alreadydescribed series of characters A, B, C, D, It is assumed that therelevant register of the data store is read out in the sub-timeintervals 1.5, 2.5 and 3.5 of each cycle of the central clock. FirstFIG. 2 will be considered. In the sub-time interval 1.5 which followsthe sub-time interval 1.1 in which the character A is written in in thedata store, the character A is read out as is illustrated in FIG. 2c.Similarly, in the subsequent sub-time intervals 2.5 and 3.5 thecharacter A is read out. Due to the shift of the instant at which thecharacter B is written in, the character A is read out again in thesub-time interval 1.5 of the next cycle, so that the character A is readout four times in total. In the sub-time intervals 2.5 and 3.5 of thiscycle and in the sub-time interval 1.5 of the subsequent cycle, thecharacter B is read out and so on. In this way the series A, A, A, A, B,B, B, C, C, C, is formed. Now'FlGj 3 will be considered. In the sub-timeinterval 1.5 which follows the sub-time interval 1.1 in which thecharacter ter D is read out in the sub-time interval 3.5, so that thecharacter C in total is read out twice instead of three times. In thesub-time intervals 1.5 and 2.5 of the subsequent cycle the character Dis read out again and so on. In this way the series A, A, A, B, B, B, C,C, D, D, D, is formed.

FIG. 4 illustrates the logic diagram of a logic unit for converting themodified series read out of the data store into the original series. Itis to be noted that this logic diagram can be realized in differentmanners, for example, by a suitable programming of the control processorof the telecommunication exchange. The logic diagram is adapted to thesimplified system and the examples of the FIGS. 2 and 3.

The characters originating from the data store 107 are applied to thethree-stage shift register 401 via input terminal 400. The shift pulsesfor the shift register are derived from the output of AND-gate 402,having a first input to which the clock pulses cs are applied, and asecond input which is connected to the output of OR-gate 403. TheOR-gat'e has a first input to which the clock signal S is applied, asecond input. to which the clock signal 5 is applied anda third input towhich the clock signal 53.5 is applied. A clock pulsecs is a clock pulsewhich occurs in a sub-time interval. A clock signal S is'a 2-statesignal having the state 1 in each sub-time interval 1.5, and a clocksignal S generally is a 2-stage signal having the state 1 in eachsub-time interval i.j., i and j being arbitrary integral numbers. Due tothe action of AND-gate 402 and OR- gate 403 shift pulses are applied tothe shift register 401 only in the sub-time intervals 1.5, 2.5 and 3.5.Consequently, only the characters appearing on the input terminal 400 inthe sub-time intervals 1.5, 2.5 and 3.5 are stored in the shiftregister. Each shift pulse shifts the characters one location further inthe shift register so that each character is shifted out of the shiftregister after three shift pulses,

The three stages of the shift register 401 have individual outputs. Theoutput of the first stage and the output of the second stage areconnected to different inputs of a first comparing unit 404. The outputof the second stage and the output of the third stage are connected todifferent inputs of a second comparing unit 405. The output signal ofeach comparing unit is a 2-state signal which has the state 1 only ifthe two characters applied to the comparing unit are equal.

A pair of flipflops 406 and 407 serve for storing the states of theoutput signals of the comparing units 404 and 405. Connected between theoutputs of the comparing units and the inputs of the flip-flops are apair of AND-gates 408 and 409. AND-gate 408 has a first input which isconnected to the output of comparing unit 404, a second input which isconnected to the output of AND-gate 412, and an output which isconnected to the input of flip-flop 406. AND-gate 409 has a first inputwhich is connected to the output of comparing unit 405, a. second inputwhich is connected to the output of AND-gate 412, and an output which isconnected to the input of flipflop 407. The flipflops 406 and 407 arecontrolled by the clock pulses which are derived from the output ofAND-gate 410, under the control of which the state of the output signalsof the AND-gates 408 and 409 is stored in the flip-flops. AND-gate 410has a first input which isconnected to the output of OR-gate 411, and asecond input to which the clock pulses cs are applied. OR-gate 411 has afirst input for the clock signal S a second input for the clock signalsS and a third input for the clock signal 8 Due to the action of theAND-gates 408, 409 and 410 and of OR-gate 411, the states of the outputsignals of the comparing units 404 and 405 are stored in the flipflops406 and 407 in the sub-time intervals 1.6, 2.6 and 3.6, provided thatthe output signal of AND-gate 412 has the state 1 in these sub-timeintervals. If the output signal of AND-gate 412 has the state 0 in thesesub-time intervals, the flip-flops 406 and 407 are reset to the state 0.The latter is dependent of the result of preceding comparisons, as willbe described hereinafter. v

Each of, the flipflops 406 and 407 hastwo outputs which are denotedinthe Figure by the references 1 and 0. These outputs supply inverse2-stage signals. The 1- output supplies a 2-stage signal which has thestate 1, when the state ,1 is stored in the fiipflop. The 0- output thensupplies a signal having the state0. The l-outputs of the flipflops 406and 407 are connected to differentinputs of AND-gate 413. The 0-outputof flipflop 406 and the l-output of flipflop 407 are connected todifferent inputs of AND-gate 413. The 0-output of fliptlop 406 and thel-output of flipflop 407 are connected to different inputs of AND-gate414.

The output of AND-gate 413 is connected to the input of flipflop 415,the l-output of which is connected to the input of flipflop 416. Theoutput of AND- gate 414 is connected to the input of flipflop 417. The

. clock pulses for controlling the flipflops 415, 416 and 417 arederived from the output of AND-gate 418. This AND-gate has a first inputto which the clock pulses cs are applied, and a second input which isconnected to the output of OR-gate 419. This OR-gate has three differentinputs to which the clock pulses S S and S respectively, are applied.The result of the action of AND-gate 418 and OR-gate 419 is that in thesub-time intervals 2.1, 3.1 and 4.1 clock pulses are applied to theflipflops .415, 416 and 417. The O-outputs of the flipflops 415, 416 and417 are connected to different inputs of AND-gate 412. The resultthereof is that the output signal of OR-gate 412 has the state 1 only ifall flipflops 415, 416 and 417 are in the state 0."

A second shift register 420 serves for storing the original series ofcharacters. The input of shift register 420 is connected to the outputof the second state of shift register 401. The shift pulses for shiftregister 420 are derived from the output of AND-gate 421. This AND- gatehas a first input which is connected to the output of AND-gate 402, anda second input which is connected to the output of OR-gate 422. ThisOR-gate has a first input which is connected to the l-output of flipflop415, and a second input which is connected to the l-output of flipflop417. Due to the action of OR-gate 422 and AND-gate-42l, shift pulses areapplied to shift register 420 in the sub-time intervals 1.5, 2.5 and3.5, provided that flipflop 415 or flipflop 417 is in the state is 1.77

Hereinafter x represents a variable which cyclically assumes the values1, 2 and 3 in time, x 1 represents the value succeeding the value ofx, x2 represents the value succeeding the value ofx l, and so on.

The operation of the device shown in FIG. 4 is as follows. In eachsub-time interval x.5 a shift pulse is applied to the shift register401, so that a character is shifted into the first stage and allcharacters in the shift register are shifted one location. In thesubsequent subtime interval x.6 the states of the comparison units 404and 405 are taken over by the flipfiops 406 and 407. This continuesuntil flipflop 407 is set to the state 1, which is the case when, aftera shift is shift register 401, the character of the second stage is thesame as the character of the third stage. Two cases can bedistinguished. In the first case flipflop 406 remains in the state whenflipflop 407 is set to the state 1, and in the second case flipflop 406is set to the state I simultaneously with flipflop 407. In the firstcase flipflop 417 is set to the state "1 in a sub-time interval (.r +1).1 under the control of AND-gate 414.

Flipfiop 417 then actuates the AND-gate 421 via OR- gate 422, so that inthe first of the sub-time intervals (.r H5 which follows the lattersub-time interval (x l).l the character of the second stage of shiftregister 401 is transferred to shift register 420. Furthermore, flipflop417 sets the output signals of the AND-gates 408 and 409 to the state 0"via AND-gate 412, so that in the sub-time interval (.r l).6 whichfollows the latter sub-time interval (.r l ).5 the flipflops 406 and-407are reset to the state 0. As a result, flipflop 417 is reset to thestate 0 in the first of the sub-time intervals (.r 2).1 which followsthe latter sub-timeinterval (.r +1 ).6. In the first of the sub-timeintervals (.r 2).5 which follows the latter sub-time interval (x 2).1the AND-gate 421 is inoperative and no character is transferred toregister 420. After a character has been transferred, the transfer isblocked once, independent of the states of the comparison units 404 and405.

In the second of the above-mentioned cases the flipflop 415 is set tothe state 1" in a sub-time interval (.r l ).1. This flipflop has thesame operation as flipflop 417 so that a character is transferred toregister 420 and the flipflops 406 and 407 are reset to the state 0. Inthe first ofthe sub-time intervals (.r-l- 2).1 which follows the lattersub-time interval (1' l).l, the flipflop 415 is reset to the state 0,and flipflop 416 is set to the state 1. As a result, the flipflops 406and 407 remain in the state 0 in the first of the sub-time intervals (x2).6 which follows the latter sub-time interval (.r 2).1. The AND-gate421 is then operative in the first of the sub-time intervals (x 3).5which follows the latter sub-time interval (x 2 ).6, so that nocharacter is transferred to register 420. After a character has beentransferred, the transfer is blocket twice in this 10 second case,independent of the state of the comparison units 404 and 405.

The first time that equality is detected between the characters of thesecond and the third stage after a shift in shift register 401, thecharacter of the second stage is transferred to shift register 420.After the next shift in shift register 401, the states of the comparisonunits 404 and 405 are not taken over by the flipflops 406 and 407. As aresult, flipflops 415 and 417 remain in the state 0, and AND-gate 421remains blocked via OR- gate 422, so that no character is transferred toshift register 420. In other words: after each transfer of a characterthe transfer is unconditionally blocked once. If equality is alsodetected between the characters of the first and the second stage ofshift register 401 prior to the transfer of a character, the states ofthe comparison units 404 and 405 are not taken over by the flipflops 406and 407 twice in succession. After the transfer of a character, thetransfer is then unconditionally blocked twice in succession.

The operationof the device according to FIG. 4 upon reception of theseries A, A, A, B, B, B, B, C, C, C, D, D, D, is illustrated in thetable of FIG. 5. The columns 1, 2 and 3 correspond to the first, thesecond and the third stage of shift register 401, respectively. Thecolumns 4, 5, 6 and 7 correspond to the first, the second, the third andthe fourth stage, respectively, of shift register 420. Each lineshowsthe contents of the stages of the shift registers at a given instant.Shift register 401 reaches the state of line 1 after three shiftsfollowing the start of the series. In this state equality is detectedbetweenthe characters of the columns 2 and 3 and those of the columns 1and 2. The character A of column 2 is transferred to shift register 420.The transfer is subsequently unconditionally blocked twice insuccession, so that after the states of the lines 2 and 3 have beenreached, no character is tranferred. After the state of line 4 has beenreached, the character B is tranferred to shift register 420 and thecontents thereof are shifted, one location further. The transfer issubsequently unconditionally blocked twice in succession '(1ines5 and6). In the state of line 7 no equality is detected between thecharacters of the columns 2 and 3, so that also in this case no transferis effected. After the state of line 8 has been reached, the character Cof column 2 is transferred to the shift register 420, and so on. Afterthe state of line 11 has been reached and the subsequent transfer of thecharacter D has been effected, the original series is stored in theshift register 420.

In the table of FIG. 6 the corresponding operation is illustrated whicha series A, A, A, B, B, C, C, C, D, D, D, is received. With respect toFIG. 5 it is to be noted that in the state of line.4 equality isdetected only between the characters of the columns 2 and 3, so thatafter the transfer of the character B of column 2 to shift register 420the transfer is unconditionally blocked only once.

What is claimed is:

l. A device for transferring information from a first channel in theform of a first cycle of channel intervals to a second channel in theform of a second cycle of channel intervals where the nominal durationof the first cycle of channel intervals is equal to the nominal durationof the second cycle of channel intervals, comprising a data register,synchronization means connected to the first channel for sequentiallyproviding the information of the first channel to the data register 1 1in channel intervals of the second cycle shifted within the second cycleof channel intervals by an amount corresponding to the phase shiftbetween the first cycle of channel intervals and the second cycle ofchannel intervals, scanning means for non-destructively reading out thedata register at least three times in each second cycle of channelintervals thereby forming multiple information words, means forsequentially storing the scanned information, comparator means forproviding a control signal in response to a condition wherein the storedscanned information is identical to the preceding stored scannedinformation, and logic means responsive to the control signal fortransferring the stored scanned information into the second channel onetime in response to at most (11 l successive control signals where n isan integer greater than 2 and is equal to the number of times thescanning means reads out the data register in each second cycle ofchannel intervals 2. A device as claimed in claim 1, wherein the logicmeans comprises a second comparator means for providing a second controlsignal in response to a condition wherein the stored scanned informationis identical to the succeeding stored scanned information, a first logicgate responsive to a coincidence between the first control signal andthe absence of a blocking signal for transferring the stored scannedinformation to the second channel, and a second logic gate means forpro.- viding the blocking signal for the duration of the next succeedingstored scanned information in response to the transfer of the storedscanned information and for providing a blocking signal for the durationof the next two succeeding information signals in response to acoincidence between the second control signal and a transfer of thestored scanned information.

1. A device for transferring information from a first channel in theform of a first cycle of channel intervals to a second channel in theform of a second cycle of channel intervals where the nominal durationof the first cycle of channel intervals is equal to the nominal durationof the second cycle of channel intervals, comprising a data register,synchronization means connected to the first channel for sequentiallyproviding the information of the first channel to the data register inchannel intervals of the second cycle shifted within the second cycle ofchannel intervals by an amount corresponding to the phase shift betweenthe first cycle of channel intervals and the second cycle of channelintervals, scanning means for non-destructively reading out the dataregister at least three times in each second cycle of channel intervalsthereby forming multiple information words, means for sequentiallystoring the scanned information, comparator means for providing acontrol signal in response to a condition wherein the stored scannedinformation is identical to the preceding stored scanned information,and logic means responsive to the control signal for transferring thestored scanned information into the second channel one time in responseto at most (n + 1) successive control signals where n is an integergreater than 2 and is equal to the number of times the scanning meansreads out the data register in each second cycle of channel intervals.2. A device as claimed in claim 1, wherein the logic means comprises asecond comparator means for providing a second control signal inresponse to a condition wherein the stored scanned information isidentical to the succeeding stored scanned information, a first logicgate responsive to a coincidence between the first control signal andthe absence of a blocking signal for transferring the stored scannedinformation to the second channel, and a second logic gate means forproviding the blocking signal for the duration of the next succeedingstored scanned information in response to the transfer of the storedscanned information and for providing a blocking signal for the durationof the next two succeeding information signals in response to acoincidence between the second control signal and a transfer of thestored scanned information.